Semiconductor device and integrated circuit including the semiconductor device

ABSTRACT

A semiconductor device includes a source metallization and a semiconductor body. The semiconductor body includes a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization. The semiconductor body also includes a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization. A voltage tap including a semiconductor region within the semiconductor body is electrically coupled to a first gate electrode of the first field-effect structure by an intermediate inverter structure.

BACKGROUND

Field-effect controlled power switching structures such as a Metal Oxide Semiconductor Field-effect Transistors (MOSFETs) or an Insulated Gate Bipolar Transistors (IGBTs) have been used for various applications including but not limited to switches in power supplies and power converters, e.g., half-bridges.

The direction of current flow through the field-effect controlled structures operating as switches is different in different operating cycles. In an on/off-mode or forward mode of the field-effect controlled structure, a pn-body diode at a body-drain junction of the field-effect controlled structure is reversely biased and the resistance of the device can be controlled by the voltage applied to the gate electrode of the field-effect controlled device. In a diode mode of the field-effect controlled device, the pn-body diode is forward biased. This results in a loss which is mainly determined by the product of current flow and voltage drop across the body diode. The pn-body diode may be forward biased when switching inductive loads, for example.

In view of meeting the demands on electrical characteristics of field-effect controlled power switching structures, it is desirable to reduce switching losses of the pn-body diode in field-effect controlled power switching structures.

SUMMARY

According to a first embodiment of a semiconductor device, the semiconductor device includes a source metallization and a semiconductor body. The semiconductor body includes a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization. The semiconductor body further includes a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization. A voltage tap including a semiconductor region within the semiconductor body is electrically coupled to a first gate electrode of the first field-effect structure by an intermediate inverter structure.

According to a second embodiment of a semiconductor device, the semiconductor device includes a source metallization and a semiconductor body. The semiconductor body includes a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization. The semiconductor body further includes a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization. A first gate electrode of the first field-effect structure is electrically coupled to a first gate driver circuit and a second gate electrode of the second field-effect structure is electrically coupled to a second gate driver circuit different from the first gate driver circuit. The first field-effect structure and the second field-effect structure share a common drain.

According to a first embodiment of an integrated circuit, the integrated circuit includes a half-bridge circuit. The half-bridge includes the semiconductor device of the first embodiment.

According to a second embodiment of an integrated circuit, the integrated circuit includes a half-bridge circuit. The half-bridge includes the semiconductor device of the second embodiment.

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other.

Embodiments are depicted in the drawings and are detailed in the description which follows.

FIG. 1 is a schematic illustration of a vertical cross section through a part of a MOSFET including first and second field effect structures, wherein a gate electrode of the first field electrode structures is electrically coupled to a guard ring in an edge termination area.

FIG. 2 is a schematic illustration of a junction termination extension (JTE) structure in the edge termination area as an alternative to the guard ring edge termination of the MOSFET illustrated in FIG, 1.

FIG. 3 is a schematic illustration of a vertical cross section through a part of the cell area of the MOSFET illustrated in FIG. 1 including a first transistor cell and a second transistor cell.

FIG. 4 is a schematic illustration of a vertical cross section through a part of a MOSFET including first and second field-effect structures, wherein a gate electrode of the first field electrode structures is electrically coupled to a source of a depletion transistor.

FIG. 5 is a schematic illustration of a vertical cross section through a part of a MOSFET including a first gate electrode of a first field-effect structure electrically coupled to a first gate driver circuit and a second gate electrode of the second field-effect structure electrically coupled to a second gate driver circuit different from the first gate driver circuit.

FIG. 6 is a schematic illustration of one part of an integrated circuit including a half-bridge circuit.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, an in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, “leading”, “trailing”, “over”, “above”, “below”, etc., is used with reference to the orientation of the Figure(s) being described. Because components of the embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention include such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing processes have been designated by the same references in the different drawings if not stated otherwise.

The terms “lateral” and “horizontal” as used in this specification intends to describe an orientation parallel to a first surface of a semiconductor substrate or semiconductor body. This can be for instance the surface of a wafer or a die.

The term “vertical” as used in this specification intends to describe an orientation which is arranged perpendicular to the first surface of the semiconductor substrate or semiconductor body.

As employed in this specification, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together—intervening elements may be provided between the “coupled” or “electrically coupled” elements.

In this specification, n-doped may refer to a first conductivity type while p-doped is referred to a second conductivity type. It goes without saying that the semiconductor devices can be formed with opposite doping relations so that the first conductivity type can be p-doped and the second conductivity type can be n-doped. Furthermore, some Figures illustrate relative doping concentrations by indicating “⁻” or “⁺” next to the doping type. For example, “n⁻” means a doping concentration which is less than the doping concentration of an “n”-doping region while an “n⁺”-doping region has a larger doping concentration than the “n”-doping region. Indicating the relative doping concentration does not, however, mean that doping regions of the same relative doping concentration have the same absolute doping concentration unless otherwise stated. For example, two different n⁺ regions can have different absolute doping concentrations. The same applies, for example, to an n⁺ and a p⁺ region.

Specific embodiments described in this specification pertain to, without being limited thereto, power semiconductor devices which are controlled by field-effect and particularly

to unipolar devices such as MOSFETs, bipolar devices such as IGBTs and unipolar and bipolar devices having compensation structures such as Superjunction-MOSFETs.

The term “field-effect” as used in this specification intends to describe the electric field mediated formation of an “inversion channel” and/or control of conductivity and/or shape of the inversion channel in a semiconductor region of the second conductivity type. Typically, the semiconductor region of the second conductivity type is arranged between two semiconductor regions of the first conductivity type and a unipolar current path through a channel region between the two semiconductor regions of the first conductivity type is formed and/or controlled by the electric field. The conductivity type of the channel region is typically changed to the first conductivity type, i.e., inverted, for forming the unipolar current path between the two semiconductor regions of the first conductivity type.

In the context of the present specification, the semiconductor region of the second conductivity type in which an inversion channel can be formed and/or controlled by the field-effect is also referred to as body region.

In the context of the present specification, the term “field-effect structure” intends to describe a structure which is formed in a semiconductor substrate or semiconductor body or semiconductor device and has a gate electrode which is insulated at least from the body region by a dielectric region or dielectric layer. Examples of dielectric materials for forming a dielectric region or dielectric layer between the gate electrode and the body region include, without being limited thereto, silicon oxide (SiO₂), silicon nitride (Si₃N₄), silicon oxinitride (SiO_(x)N_(y)), zirconium oxide (ZrO₂), tantalum oxide (Ta₂O₅), titanium oxide (TiO₂) and hafnium oxide (HfO₂) or stacks of two or more of the aforementioned materials.

Above a threshold voltage V_(th) between the gate electrode and the body region, an inversion channel is formed and/or controlled due to the field-effect in a channel region of the body region adjoining the dielectric region or dielectric layer. The threshold voltage V_(th) typically refers to the minimum gate voltage necessary for the onset of a unipolar current flow between the source and the drain of a transistor.

In the context of the present specification, devices such as MOS-controlled diodes (MCDs), MOSFETs, IGBTs and devices having compensation structures such as Superjunction-MOSFETs as well as integrated devices with different field-effect structures are also referred to as field-effect structures.

In the context of the present specification, the term “MOS” (metal-oxide-semiconductor) should be understood as including the more general term “MIS” (metal-insulator-semiconductor). For example, the term MOSFET (metal-oxide-semiconductor field-effect transistor) should be understood to include FETs having a gate insulator that is not an oxide, i.e., the term MOSFET is used in the more general term meaning IGFET (insulated-gate field-effect transistor) and MISFET, respectively.

In the context of the present specification, the terms “metal” and “metallization” should be understood as including the more general term conductor. For example, the material of a gate electrode has not necessarily to be made out of metal but can also be made of any conducting material like e.g. a semiconductor layer or a metal-semiconductor compound or any other suitable material.

Further, terms such as “first”, “second”, and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

FIG. 1 schematically illustrates a vertical cross section through a part of a normally-off or enhancement mode MOSFET 100 according to an embodiment. The MOSFET 100 includes an n-type semiconductor body 101 with a first surface 102 and a second surface 103. The first surface 102 may be at a front side of the semiconductor body 101 and the second surface 103 may be at a rear side of the semiconductor body 101. FIG. 1 illustrates the cross-section in a vertical section plane which extends perpendicular to the first and second surfaces 102, 103.

The MOSFET 100 includes an edge termination area 104 and a cell area 105. In the embodiment illustrated in FIG. 1, the edge termination area 104 includes multiple floating p-type guard rings 106 a, 106 b, 106 c. The guard rings 106 a, 106 b, 106 c serve to reduce the amount of electric field crowding at a main pn-junction in the cell area 105 by spreading the depletion layer past consecutively lower potential floating junctions of the guard rings 106 a, 106 b, 106 c. These independent junctions act to increase the depletion layer spreading, thereby decreasing the high electric field at the main pn-junction in the cell area 105.

According to one embodiment, the guard rings 106 a, 106 b, 106 c are fabricated simultaneously with semiconductor regions in the cell area 105. As an example, the guard rings 106 a, 106 b, 106 c may be fabricated simultaneously with a body region in the cell area 105 of the MOSFET 100. According to another embodiment, the guard rings 106 a, 106 b, 106 c may be fabricated independently from semiconductor regions in the cell area. For illustration purposes, a number n of the guard rings 106 a, 106 b, 106 c illustrated in FIG. 1 is 3. However, a different number n of the guard rings may be used such as n=1, 2, 4, 5, 6, 7, 8, for example. Widths w_(a), w_(b), w_(c) of the guard rings 106 a, 106 b, 106 c may match, differ or partly differ. Similarly, distances d_(cb) and d_(ba) between the guard rings 106 c, 106 b and 106 b, 106 a may also match or differ.

The cell area 105 includes p-type body regions 107 a, 107 b and n⁺-type source regions 108 a, 108 b, 108 c. The p-type body regions 107 a, 107 b and the n⁺-type source regions 108a, 108 b, 108 c are short-circuited via contacts 109 a, 109 b and a source metallization 110. A bottom side of the body regions 107 a, 107 b adjoins to p-type compensation zones 111 a, 111 b, respectively. Between the p-type compensation zones 111 a, 111 b, an n-type drift zone constituting part of the semiconductor body 101 is arranged. The n-type drift zone adjoins to an n⁺-type drain region 112 at the second surface 103.

First gate structures 113 a, 113 b including first gate insulating layers 114 a, 114 b and first gate electrodes 115 a, 115 b are arranged on the body regions 107 a, 107 b at the first surface 102. The guard ring 106 a in the edge termination area 104 is electrically coupled to the first gate electrodes 115 a, 115 b by an inverter structure 160 and a wiring 116. The wiring 116 is illustrated in a simplified manner and may include contact(s) and metal line(s). The inverter structure 160 may be formed as a CMOS (Complementary Metal Oxide Semiconductor) inverter, a bipolar inverter, a BiCMOS (Bipolar CMOS) inverter, an NMOS (n-channel MOS) inverter, a PMOS (p-channel MOS) inverter, for example. The inverter structure may be formed in a part of the semiconductor body 101 different from the part illustrated in FIG. 1, for example. The inverter structure 160 is a device configured to convert the potential in the guard ring 106 a to a potential suitable of driving the first gate electrodes 115 a, 115 b. According to one embodiment, for example, when the potential of the guard ring 106 a is more negative than the potential of the source metallization 110, the inverter structure 160 may apply a positive voltage to the first gate electrodes 115 a, 115 b, the positive voltage being related to the potential of the source metallization 110. When the potential of the guard ring 106 a is more positive than that the potential of the source metallization 110, the inverter structure 160 may apply a voltage lower than or close to the voltage of the source metallization 110 to the first gate electrodes 115 a, 115 b. According to another embodiment, when the potential of the guard ring 106 a falls below a threshold value related to the potential of the source metallization 110, the inverter structure 160 may apply a voltage close to the voltage of the source metallization 110 or a positive voltage to the first gate electrodes 115 a, 115 b. When the voltage of the guard ring 106 a rises above this threshold voltage, a negative voltage related to the voltage of the source metallization 110 may be applied to the first gate electrodes 115 a, 115 b.

In the embodiment illustrated in FIG. 1, the first gate electrodes 115 a, 115 b are electrically coupled to the guard ring 106 a. According to another embodiment, the first gate electrodes 115 a, 115 b are electrically coupled to another one of the guard rings.

A second gate structure 117 a including a second gate insulating layer 118 a and a second gate electrode 119 a is arranged on the body region 107 b at the first surface 102. The second gate electrode 119 a is electrically coupled to a gate driving circuit (not illustrated in FIG. 1). Hence, the first gate electrodes 115 a, 115 b are electrically disconnected from the second gate electrode 119 a. In other words, there is no low ohmic electrical connection between the first gate electrodes 115 a, 115 b and the second gate electrode 119 a.

First field-effect structures 120 a, 120 b, which are normally-off, include the first gate structures 113 a, 113 b, the source regions 108 a, 108 c and a part of the body regions 107 a, 107 b. A second field-effect structure 121 a, which is normally-off, includes the second gate structure 117 a, the source region 108 b and another part of the body region 107 b. Both the first field-effect structures 120 a, 120 b and the second field-effect structure 121 a share the drift zone and the drain region 112.

The first field-effect structures 120 a, 120 b are called MOS gated diodes (MGD) in the following and are electrically drivable independently from the second field-effect structure 121 a. In the embodiment illustrated in FIG. 1, the first gate electrodes 115 a, 115 b are electrically coupled to the guard ring 106 a in the edge termination area 104 via the inverter structure 160. The guard ring 106 a is electrically disconnected from a gate driving circuit to which the second gate electrode 119 a is electrically coupled. The schematic illustration of FIG. 1 only covers a part of the cell area 105. The overall cell area includes a plurality of the first field-effect structures and a plurality of the second field-effect structures. According to one embodiment, a number of the first field-effect structures in the overall cell area is smaller than the number of the second the second field-effect structures in the overall cell area.

When the MOSFET 100 is turned on, a body diode formed by the body regions 107 a, 107 b and the drift zone/drain region 112 is reversely biased by a small voltage V₁ and the second field-effect structure 121 a can control a conductivity of a channel region between source and drain of the MOSFET 100 by the field-effect. Therefore, the second field-effect structure 121 a is also referred to as a controllable field-effect structure. To control the conductivity of the channel region, an appropriate voltage is applied to the second gate electrode 119 a to induce an inversion channel within the body regions 107 b at the first surface 102 adjoining to the second gate structure 117 a. In this mode, the electric potential of the guard ring 106 a is electrically coupled to the first gate structures 113 a, 113 b by the inverter structure 160 also turning the first field-effect structures 120 a, 120 b on, i.e. the guard ring 106 a provides a low level signal to the inverter structure 160 which is inverted to a high level signal supplied to the first gate structures 113 a, 113 b and turning on the normally-off first field-effect structures 120 a, 120 b. Thus, a load current is shared by the second field-effect structure 121 a and the first field-effect structures 120 a, 120 b in this operation mode.

When the body diode of the MOSFET 100 is turned on, e.g. during switching of an inductive load, the body diode formed by the body regions 107 a, 107 b and the drift zone/drain region 112 is forwardly biased by a small voltage V₂ and the second field-effect structure 121 a is turned off by an appropriate turn off signal at the second gate electrode 119 a. In this mode, the electric potential of the guard ring 106 a is electrically coupled to the first gate structures 113 a, 113 b by the inverter structure 160 turning the first field-effect structures 120 a, 120 b on, i.e. the guard ring 106 a provides a low level signal to the inverter structure 160 which is inverted to a high level signal supplied to the first gate structures 113 a, 113 b and turning on the normally-off first field-effect structures 120 a, 120 b. Thus, a current path between source and drain of the first field-effect structures 120 a, 120 b is in parallel to a diode current flowing between the body regions 107 a, 107 b and the drift zone/drain region 112. This additional current path between source and drain of the first field-effect structures 120 a, 120 b leads to a reduction of the resistance of the body diode. Hence, switching losses determined by the product of current flow and voltage drop across the body diode can be decreased.

In a static blocking mode of the MOSFET 100, the body diode is reversely biased by a large voltage V₃, |V₃|>>|V₁|, and the second field-effect structure 121 a is turned off by an appropriate signal at the second gate electrode 119 a. In this mode, the electric potential of the guard ring 106 a is electrically coupled to the first gate structures 113 a, 113 b by the inverter structure 160 turning the first field-effect structures 120 a, 120 b off, i.e. the guard ring 106 a provides a high level signal to the inverter structure 160 which is inverted to a low level signal supplied to the first gate structures 113 a, 113 b and turning off the normally-off first field-effect structures 120 a, 120 b.

According to another embodiment, each voltage of the guard ring 106 a above or equal to the potential of the source regions 108 a, 108 b, 108 c may cause an appropriate low level signal at the output of the inverter structure 160 which is supplied to the first gate structures 113 a, 113 b for turning off the normally-off first field-effect structures 120 a, 120 b. In other words, the first field-effect structures 120 a, 120 b may be only in a conducting mode or turned on when the body diode is in a conducting mode and the first field-effect structures 120 a, 120 b may be in a blocking mode or turned off when the MOSFET 100 is in a conducting mode or when the body diode is in non-conducting mode.

FIG. 2 schematically illustrates a Junction Termination Extension (JTE) structure in the edge termination area 104 of the MOSFET 100 as an alternative to the guard rings of the embodiment illustrated in FIG. 1. The JTE structure includes a first p-type zone 125 adjoining to the first surface 102. The first p-type zone 125 serves to reduce the amount of electric field crowding at the main pn-junction in the cell area 105 by increasing the depletion layer spreading, thereby decreasing the high electric field at the main pn-junction in the cell area 105. Variation Lateral Doping (VLD) may be used for the JTE structure.

The wiring 116 and the inverter structure 160 electrically couple a voltage tap including a second p-type zone 126 to the first gate electrodes 115 a, 115 b of the first field-effect structures 120 a, 120 b (not illustrated in FIG. 2, cf. FIG. 1). The second p-type zone 126 is arranged within the first p-type zone 125 of the JTE structure and may constitute part of the first p-type zone 125.

According to other embodiments, edge termination structures different from the ones illustrated in FIGS. 1 and 2 may be used, e.g. a combination of a selection or all of field plates, JTE-structures, VLD-structures and guard rings.

FIG. 3 schematically illustrates a vertical cross section through a part of the cell area 105 of the MOSFET 100 illustrated in FIG. 1. The cell area 105 includes a first transistor cell 130 and a second transistor cell 131. Whereas the first transistor cell 130 includes a first gate structure 113 c similar to the gate structures 113 a, 113 b illustrated in FIG. 1 and a second gate structure 117 b similar to the gate structure 117 a illustrated in FIG. 1, the second transistor cell 131 includes only second gate structures 117 c, 117 d similar to the gate structure 117 a illustrated in FIG. 1. Thus, only the first transistor cell 130 includes a gate electrode, i.e. the gate electrode 115 c, that is electrically coupled to a voltage tap in the edge termination area 104 by the wiring 116 and the inverter structure 160 (not illustrated in FIG. 3).

According to one embodiment, 5% to 60% of cells of the cell area 105 include both the first field-effect structure and the second field-effect structure similar to the first transistor cell 130 illustrated in FIG. 3. The remaining cells of the cell area 105 include the second field-effect structure but not the first field-effect structure similar to the second transistor cell 131 illustrated in FIG. 3.

FIG. 4 schematically illustrates a vertical cross section though a part of a MOSFET 200 according to another embodiment. The MOSFET 200 includes an n-type semiconductor body 201 with a first surface 202 and a second surface 203. The first surface 202 may be at a front side of the semiconductor body 201 and the second surface 203 may be at a rear side of the semiconductor body 201. FIG. 4 illustrates the cross section in a vertical section plane which extends perpendicular to the first and second surfaces 202, 103.

The MOSFET 200 includes a cell area 205. The cell area 205 includes p-type body regions 207 a, 207 b, 207 c and n⁺-type source regions 208 a, 208 b, 208 c, 208 d. The p-type body regions 207 a, 207 b, 207 c and the n⁺-type source regions 208 a, 208 b, 208 c, 208 d are short-circuited. The short-circuit is illustrated in simplified manner by an interconnection 236 which includes a source metallization.

A first gate structure 213 a including a first gate insulating layer 214 a and a first gate electrode 215 a is arranged in a trench 235 a extending into the semiconductor body 201 from the first surface 202. The first gate insulating layer 214 a is part of a dielectric structure 237 a within the trench 235 a. The first gate electrode 215 a is electrically coupled to a source region 238 a of a depletion transistor 240 by a wiring 216 and an inverter structure 260, which are illustrated in a simplified manner and may include contact(s), active semiconductor devices like e.g. transistors, and metal line(s).

A second gate structure 217 a including a second gate insulating layer 218 a and a second gate electrode 219 a is arranged in a trench 235 b extending into the semiconductor body 201 from the first surface 202 similar to the trench 235 a. The second gate insulating layer 218 a is part of a dielectric structure 237 b within the trench 235 b. The second gate electrode 219 a is electrically coupled to a gate driving circuit (not illustrated in FIG. 4). Hence, the first gate electrode 215 a is electrically disconnected from the second gate electrode 219 a.

A first field-effect structure 220 a includes the first gate structure 213 a, the source regions 208 a, 208 b and a part of the body regions 207 a, 207 b. A second field-effect structure 221 a includes the second gate structure 217 a, the source regions 208 c, 208 d, another part of the body region 207 b and a part of the body region 207 c. Both the first field-effect structure 220 a and the second field-effect structure 221 a share a drift zone constituting part of the semiconductor body 201 and an n⁺-type drain region 212.

Third gate structures 247 a, 247 b of the depletion transistor 240 include third gate insulating layers 248 a, 248 b and third gate electrodes 249 a, 249 b. The third gate insulating layers 248 a, 248 b are part of dielectric structures 256 a, 256 b within trenches 235 c, 235 d. A p-type discharge region 251 is electrically coupled to a terminal for a reference potential V_(Ref). In the embodiment illustrated in FIG. 4, the discharge region 251 is arranged distant to the source region 238 a and is arranged adjacent the third gate electrode 249 b, or, more precisely, the third gate insulating layer 248 b. In the embodiment illustrated in FIG. 4 the discharge region 251 is arranged directly below the first surface 202 and is separated from the source region 238 a and a channel region 252 through the third gate electrode 249 b and the third gate insulating layer 248 b, respectively. The third gate structures 247 a, 247 b are electrically coupled to a reference potential, e.g. to a source potential of the source regions 208 a, 208 b, 208 c, 208 d.

When the MOSFET 200 is turned on, a body diode formed by the body regions 207 a, 207 b, 207 c and the drift zone/drain region 212 is reversely biased by a small voltage V₁ and the second field-effect structure 221 a can control a conductivity of a channel region between source and drain of the MOSFET 200 by the field-effect. Therefore, the second field-effect structure 221 a is also referred to as a controllable field-effect structure. To control the conductivity of the channel region, an appropriate voltage is applied to the second gate electrode 219 a to induce an inversion channel within the body regions 207 b, 207 c at side walls of the trench 235 b. In this mode, the electric potential of the source region 238 a of the depletion transistor 240 is electrically coupled to the first gate structure 213 a by the inverter structure 260 also turning the first field-effect structure 220 a on, i.e. the source region 238 a of the depletion transistor 240 provides a low level signal to the inverter structure 260 which is inverted to a high level signal supplied to the first gate structure 113 a and turning on the normally-off first field-effect structure 220 a. Thus, a load current is shared by the second field-effect structure 221 a and the first field-effect structures 220 a in this operation mode.

When the body diode of the MOSFET 200 is turned on, e.g. during switching of an inductive load, the body diode formed by the body regions 207 a, 207 b, 207 c and the drift zone/drain region 212 is forwardly biased by a small voltage V₂ and the second field-effect structure 221 a is turned off by an appropriate turn off signal at the second gate electrode 219 a. In this mode, the electric potential of the source region 238 a of the depletion transistor 240 is electrically coupled to the first gate structure 213 a by the inverter structure 260 turning the first field-effect structure 220 a on, i.e. the source region 238 a of the depletion transistor 240 provides a low level signal to the inverter structure 260 which is inverted to a high level signal supplied to the first gate structure 213 a and turning on the normally-off first field-effect structure 220 a. Thus, a current path between source and drain of the first field-effect structures 220 a is in parallel to a diode current flowing between the body regions 207 a, 207 b, 207 c and the drift zone/drain region 212. This additional current path between source and drain of the first field-effect structure 220 a leads to a reduction of the resistance of the body diode. Hence, switching losses determined by the product of current flow and voltage drop across the body diode can be decreased.

In a static blocking mode of the MOSFET 200, the body diode is reversely biased by a large voltage V₃, |V₃|>>|V₁|, and the second field-effect structure 221 a is turned off by an appropriate signal at the second gate electrode 219 a. In this mode, the electric potential of the source region 238 a of the depletion transistor 240 is electrically coupled to the first gate structure 213 a by the inverter structure 260 turning the first field-effect structure 220 a off, i.e. the source region 238 a of the depletion transistor 240 provides a high level signal to the inverter structure 260 which is inverted to a low level signal supplied to the first gate structure 213 a and turning off the normally-off first field-effect structure 220 a.

According to another embodiment, each voltage of the source region 238 a of the depletion transistor 240 above or equal to the potential of the source regions 208 a, 208 b, 208 c, 208 d may cause an appropriate low level signal at the output of the inverter structure 260 supplied to the first gate structures 213 a for turning off the normally-off first field-effect structure 220 a. In other words, the first field-effect structure 220 a may be only in a conducting mode or turned on when the body diode is in a conducting mode and the first field-effect structure 220 a may be in a blocking mode or turned off when the MOSFET 200 is in a conducting mode or when the body diode is a non-conducting mode.

FIG. 5 schematically illustrates a vertical cross section through a part of a MOSFET 100′ according to another embodiment. The MOSFET 100′ is similar to the MOSFET 100 illustrated in FIG. 1, and differs from the MOSFET 100 in that the first gate electrodes 115 a, 115 b of the first gate structures 113 a, 113 b are electrically coupled to a first gate driver circuit 180 and not to the guard ring 106 a as illustrated in FIG. 1. The second gate electrode 119 a of the second gate structure 117 a is electrically coupled to a second gate driver circuit 181 different from the first gate driver circuit 180. The first gate driver circuit 180 drives the first gate electrodes 115 a, 115 b with a first gate signal S_(MGD) via a first signal line 182. The second gate driver circuit 181 drives the second gate electrode 119 a with a second gate signal S_(G) via a second signal line 183.

According to one embodiment, the first signal S_(MGD) turns the first field-effect structures 120 a, 120 b on just before, e.g. 2 to 1000 ns, the second field-effect transistor 121 a switches from a blocking mode to a forward biased mode of the body diode. The first signal S_(MGD) turns the first field-effect structures 120 a, 120 b off just after, e.g. 2 to 1000 ns, the second field-effect transistor 121 a has returned into the blocking mode. This allows to reduce the losses in the forward biased mode.

According to another embodiment, turning on the first field-effect structures 120 a, 120 b is slightly delayed and effected by the first signal S_(MGD) shortly after, e.g. 2 to 1000 ns, the second field-effect structure 121 a has turned into the forward biased mode of its body diode. This allows to reduce losses during the blocking mode.

Yet another embodiment for driving the first and second field-effect structures 120 a, 120 b, 121 a may be applied to devices having a high voltage blocking capability, e.g. of more than 100 V. In these devices, a high ohmic resistance in the drift region may lead to a forward biasing voltage in the first field-effect structures 120 a, 120 b that is higher than in the second field-effect structure 121 a. In this case, the first signal S_(MGD) turns the first field-effect structures 120 a, 120 b on for reducing the flooding with electrons/holes just before the second field-effect structure 121 a switches from the forward biased mode of the body diode into the blocking mode.

The timing of driving the first and second field-effect structures 120 a, 120 b, 121 a by the first and second gate driver circuits 180, 181 can be specifc to the application and may depend upon a ratio of a loss in a forward biased mode and the loss due to leakage currents flowing in a blocking mode.

FIG. 6 schematically illustrates one part of an integrated circuit 700 including a half-bridge circuit with a first n-type channel normally-off MOSFET 701 and a second n-type channel normally-off MOSFET 702. At least one of the first and second MOSFETs 701, 702 is similar to one of the MOSFETs described in the embodiments above and includes first and second field-effect structures, wherein the gate electrodes of the first and second field-effect structures are electrically disconnected.

In the schematic illustration of FIG. 6, an inductive load is indicated by dashed lines. In this case, the second MOSFET 702 is similar to one of the MOSFETs described in the embodiments above.

It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

Although specific embodiments have been illustrated and de-scribed herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof. 

What is claimed is:
 1. A semiconductor device, comprising: a source metallization; a semiconductor body including: a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization; and a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization; and a voltage tap including a semiconductor region within the semiconductor body electrically coupled to a first gate electrode of the first field-effect structure by an intermediate inverter structure, the voltage tap being electrically coupled to only the first gate electrode with respect to the first gate electrode of the first field-effect structure and a second gate electrode of the second field-effect structure, wherein the semiconductor region of the voltage tap is an electrically floating semiconductor zone of an edge termination structure.
 2. The semiconductor device of claim 1, wherein the source regions of the first and second field-effect structures are short-circuited.
 3. The semiconductor device of claim 1, further comprising a cell array of a first plurality of the first field-effect structure and a second plurality of the second field-effect structure, wherein the second plurality is larger than the first plurality.
 4. The semiconductor device of claim 3, wherein 5% to 60% of cells of the cell array include both the first field-effect structure and the second field-effect structure, and wherein the remaining cells of the cell array include the second field-effect structure but not the first field-effect structure.
 5. The semiconductor device of claim 1, wherein: the first field-effect structure has a first capacitance including a first gate electrode, a first gate insulator and a first body region; the second field-effect structure has a second capacitance including a second gate electrode, a second gate insulator and a second body region; and the first capacitance per unit area is larger than the second capacitance per unit area.
 6. The semiconductor device of claim 5, wherein a thickness of the second gate insulator between the second gate electrode and the second body region is larger than the thickness of the first gate insulator between the first gate electrode and the first body region.
 7. The semiconductor device of claim 1, wherein the semiconductor device is a vertical metal-oxide-semiconductor field-effect transistor having a voltage blocking capability in a range of 50 V to 1500 V.
 8. The semiconductor device of claim 1, wherein the semiconductor device is part of a reverse conducting insulated gate bipolar transistor.
 9. The semiconductor device of claim 1, wherein the first field-effect structure and the second field-effect structure share a common drain.
 10. The semiconductor device of claim 1, wherein the edge termination structure is a guard ring structure.
 11. The semiconductor device of claim 1, wherein the edge termination structure is part of a junction termination extension structure.
 12. The semiconductor device of claim 1, wherein the semiconductor region of the voltage tap adjoins a surface of the semiconductor body.
 13. The semiconductor device of claim 1, wherein the voltage tap is configured to tap a voltage at a location deeper within the semiconductor body than a bottom side of a body region of the second field-effect structure.
 14. The semiconductor device of claim 1, wherein the first gate electrode of the first field-effect structure and a second gate electrode of the second field-effect structure are planar gate electrodes arranged above a surface of the semiconductor body.
 15. The semiconductor device of claim 1, wherein the voltage tap is electrically coupled to an input of the inverter structure and the first gate electrode of the first field-effect structure is electrically coupled to an output of the inverter structure.
 16. The semiconductor device of claim 1, wherein the first gate electrode of the first field-effect structure and a second gate electrode of the second field-effect structure are electrically disconnected. 